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| nt5sv8m16fs / nt5sv8m16ft 128mb synchronous dram 1 rev 1.4 08/2009 ? nanya technology corporation nanya reserves the right to change products and spe cifications without notice. features ? high performance: ? single pulsed ras interface ? fully synchronous to positive clock edge ? four banks controlled by ba0/ba1 (bank select) ? programmable cas latency: 2, 3 ? programmable burst length: 1, 2, 4, 8 or full page ? programmable wrap: sequential or interleave ? multiple burst read with single write option ? automatic and controlled precharge command ? dual data mask for byte control (x16) ? auto refresh (cbr) and self refresh ? suspend mode and power down mode ? standard power operation ? random column address every ck (1-n rule) ? single power supply, either 3.3v ? lvttl compatible ? packages: tsop-type ii ? lead-free & halogen-free product available description the nt5sv8m16fs, and nt5sv8m16ft are four-bank syn- chronous drams organized as 2mbit x 16 i/o x 4 bank . these synchronous devices achieve high-speed data t rans- fer rates of up to 166mhz by employing a pipeline c hip archi- tecture that synchronizes the output data to a syst em clock. the device is designed to comply with all jedec sta ndards set for synchronous dram products, both electricall y and mechanically. all of the control, address, and data input/out- put (i/o or dq) circuits are synchronized with the positive edge of an externally supplied clock. ras , cas , we , and cs are pulsed signals which are exam- ined at the positive edge of each externally applie d clock (ck). internal chip operating modes are defined by combina- tions of these signals and a command decoder initia tes the necessary timings for each operation. a fifteen bit address bus accepts address data in the conventional ras /cas mul- tiplexing style. twelve addresses (a0-a11) and two bank select addresses (ba0, ba1) are strobed with ras . nine col- umn addresses (a0-a8) plus bank select addresses an d a10 are strobed with cas . prior to any access operation, the cas latency, burst length, and burst sequence must be programmed into the devi ce by address inputs a0-a11, ba0, ba1 during a mode regis ter set cycle. in addition, it is possible to program a mul tiple burst sequence with single write cycle for write through cache operation. operating the four memory banks in an interleave fa shion allows random access operation to occur at a higher rate than is possible with standard drams. a sequential and gap- less data rate of up to 166mhz is possible dependin g on burst length, cas latency, and speed grade of the device. auto refresh (cbr) and self refresh operation are s up- ported. maximum operating speed cas latency pc166 (6k/6ki) pc133 (75b/75bi) 3 6 7.5 ns
nt5sv8m16fs / nt5sv8m16ft 128mb synchronous dram rev 1.4 08/2009 2 ? nanya technology corporation nanya reserves the right to change products and spe cifications without notice. nanya technology corporation hwa ya technology park 669 fu hsing 3rd rd., kueishan, taoyuan, 333, taiwan, r.o.c. tel: +886-3-328-1688 please visit our home page for more information: ww w.nanya.com ordering information organization part number package power speed grade clock frequency cl - t rcd - t rp notes 8m x 16 nt5sv8m16fs-6k 400mil 54-pin tsop ii lead-free 3.3v 166mhz-3-3-3 lead free packaging nt5sv8m16fs-6ki lead free packaging nt5sv8m16fs-75b 133mhz-3-3-3 lead free packaging nt5sv8m16fs-75bi lead free packaging nt5sv8m16ft-6k 400mil 54-pin tsop ii 166mhz-3-3-3 NT5SV8M16FT-6KI nt5sv8m16ft-75b 133mhz-3-3-3 nt5sv8m16ft-75bi cl = cas latency lead-free products are also halogen-free nt5sv8m16fs / nt5sv8m16ft 128mb synchronous dram rev 1.4 08/2009 3 ? nanya technology corporation nanya reserves the right to change products and spe cifications without notice. pin configuration - 54 pins 400 mill tsopii package nt5sv8m16fs / nt5sv8m16ft 128mb synchronous dram rev 1.4 08/2009 4 ? nanya technology corporation nanya reserves the right to change products and spe cifications without notice. pin description ck clock input dq0-dq15 data input/output cke (cke0, cke1) clock enable dqm, ldqm, udqm data mask cs chip select v dd power (+3.3v) ras row address strobe v ss ground cas column address strobe v ddq power for dqs (+3.3v) we write enable v ssq ground for dqs ba1, ba0 bank select nc no connection a0 - a11 address inputs ? ? input/output functional description symbol type polarity function ck input positive edge the system clock input. all of the sdram inputs are sampl ed on the rising edge of the clock. cke, cke0, cke1 input active high activates the ck signal when high and deactivates the ck signal when low. by deactivating the clock, cke low initiates the power down mode, suspend mode, or the self refresh mode. cs input active low cs enables the command decoder when low and disables t he command decoder when high. when the command decoder is disabled, new commands are ign ored but previous operations continue. ras , cas , we input active low when sampled at the positive rising edge of the clock, c as , ras , and we define the operation to be executed by the sdram. ba1, ba0 input ? selects which bank is to be active. a0 - a11 input ? during a bank activate command cycle, a0-a11 defines the row address (ra0-ra11) when sam- pled at the rising clock edge. during a read or write command cycle, a0-a8 defines the column address (ca0-ca8), when sam- pled at the rising clock edge. a10 is used to invoke auto-precharge operation at the end of the burst read or write cycle. if a10 is high, auto-precharge is selected and ba0, ba1 defin es the bank to be precharged. if a10 is low, autoprecharge is disabled. during a precharge command cycle, a10 is used in conjun ction with ba0, ba1 to control which bank(s) to precharge. if a10 is high, all banks will be precharged regardless of the state of bs. if a10 is low, then ba0 and ba1 are used to define which ba nk to precharge. dq0 - dq15 input- output ? data input/output pins operate in the same manner a s on conventional drams. dqm ldqm udqm input active high the data input/output mask places the dq buffers in a high impedance state when sampled high. in x16 products, the ldqm and udqm control the lower and upper byte i/o buffers, respectively. in read mode, dqm has a latency of two clock cycles and contro ls the output buffers like an output enable. dqm low turns the output buffers on and dqm high turns them off. in write mode, dqm has a latency of zero and operates as a word mask by allow ing input data to be written if it is low but blocks the write operation if dqm is high. v dd , v ss supply ? power and ground for the input buffers and th e core logic. v ddq v ssq supply ? isolated power supply and ground for the outpu t buffers to provide improved noise immunity. nt5sv8m16fs / nt5sv8m16ft 128mb synchronous dram rev 1.4 08/2009 5 ? nanya technology corporation nanya reserves the right to change products and spe cifications without notice. block diagram dq 0 dq x data input/output buffers cke buffer ck buffer cke ck cs ras cas dqm we command decoder mode register counter column address counter refresh a1 a2 a3 a4 a5 a6 a7 a10 a8 a9 a0 a11 sense amplifiers memory bank 1 cell array row decoder address buffers (15) column decoder sense amplifiers memory bank 3 cell array row decoder column decoder sense amplifiers memory bank 0 cell array row decoder column decoder sense amplifiers memory bank 2 cell array row decoder column decoder data control circuitry ba0 ba1 control signal generator cell array, per bank, for 4mb x 16 dq: 4096 row x 512 c ol x 16 dq (dq0-dq15). nt5sv8m16fs / nt5sv8m16ft 128mb synchronous dram rev 1.4 08/2009 6 ? nanya technology corporation nanya reserves the right to change products and spe cifications without notice. power on and initialization the default power on state of the mode register is supplier specific and may be undefined. the followi ng power on and initializa- tion sequence guarantees the device is precondition ed to each users specific needs. like a conventional dram, the synchronous dram must be powered up and initialized in a predefined mann er. during power on, all v dd and v ddq pins must be built up simultaneously to the specif ied voltage when the input signals are held in the ?nop? state. the power on voltage must not exceed v dd +0.3v on any of the input pins or v dd supplies. the ck signal must be started at the same time. after power on, an initial pause of 200 s is required followed by a precharge of all banks using the precharge command. to prevent data contention on the dq bus d uring power on, it is required that the dqm and cke pins be held high during the initial pause period. once all banks hav e been precharged, the mode register set command mu st be issued to ini- tialize the mode register. a minimum of two auto re fresh cycles (cbr) are also required. these may be done before or after programming the mode register. failure to follow th ese steps may lead to unpredictable start-up modes. programming the mode register for application flexibility, cas latency, burst length, burst sequence, and operati on type are user defined variables and must be programmed into the sdram mode register with a sing le mode register set command. any content of the mo de register can be altered by re-executing the mode register set co mmand. if the user chooses to modify only a subset of the mode register variables, all four variables must be redefined whe n the mode register set command is issued. after initial power up, the mode register set comma nd must be issued before read or write cycles may b egin. all banks must be in a precharged state and cke must be high at le ast one cycle before the mode register set command can be issued. the mode register set command is activated by the low s ignals of ras , cas , cs , and we at the positive edge of the clock. the address input data during this cycle defines the pa rameters to be set as shown in the mode register op eration table. a new command may be issued following the mode register s et command once a delay equal to t rsc has elapsed. cas latency the cas latency is a parameter that is used to define the delay from when a read command is registered on a r ising clock edge to when the data from that read command become s available at the outputs. the cas latency is expressed in terms of clock cycles and can have a value of 2 or 3 cycles. the value of the cas latency is determined by the speed grade of the device and the clock frequency that is used in the application. a table showing the relationship betwe en the cas latency, speed grade, and clock frequency appears in the electrica l characteristics section of this document. once th e appropriate cas latency has been selected it must be programmed int o the mode register after power up, for an explanat ion of this procedure see programming the mode register in the previous s ection. nt5sv8m16fs / nt5sv8m16ft 128mb synchronous dram rev 1.4 08/2009 7 ? nanya technology corporation nanya reserves the right to change products and spe cifications without notice. mode register operation (address input for mode set ) a11 a3 a4 a2 a1 a0 a10 a9 a8 a7 a6 a5 address bt burst length cas latency mode cas latency m6 m5 m4 latency 0 0 0 reserved 0 0 1 reserved 0 1 0 2 0 1 1 3 1 0 0 reserved 1 0 1 reserved 1 1 0 reserved 1 1 1 reserved burst length m2 m1 m0 length sequential interleave 0 0 0 1 1 0 0 1 2 2 0 1 0 4 4 0 1 1 8 8 1 0 0 reserved reserved 1 0 1 reserved reserved 1 1 0 reserved reserved 1 1 1 full page reserved burst type m3 type 0 sequential 1 interleave operation mode m14 m13 m12 m11 m10 m9 m8 m7 mode 0 0 0 0 0 0 0 0 normal 0 0 0 0 0 1 0 0 multiple burst with single write operation mode ba1 bus (ax) register(mx) ba0 nt5sv8m16fs / nt5sv8m16ft 128mb synchronous dram rev 1.4 08/2009 8 ? nanya technology corporation nanya reserves the right to change products and spe cifications without notice. burst mode operation burst mode operation is used to provide a constant flow of data to memory locations (write cycle), or from memory locations (read cycle). there are three parameters that defin e how the burst mode will operate. these parameters include burst sequence, burst length, and operation mode. the bur st sequence and burst length are programmable, and are determined by address bits a0 - a3 during the mode register set c ommand. operation mode is also programmable and is set by address bits a7 - a11, ba0, and ba1. the burst type is used to define the order in which the burst data will be delivered or stored to the sdram. two types of burst sequences are supported, sequential and interleaved . see the table below. the burst length controls the number of bits that w ill be output after a read command, or the number o f bits to be input after a write command. the burst length can be programmed t o have values of 1, 2, 4, 8 and full page sequentia l burst. burst operation mode can be normal operation or mul tiple burst with single write operation. normal ope ration implies that the device will perform burst operations on both read a nd write cycles until the desired burst length is s atisfied. multiple burst with single write operation was added to support write t hrough cache operation. here, the programmed burst length only applies to read cycles. all write cycles are single write oper ations when this mode is selected. note: page length is a function of i/o organization and c olumn addressing. x16 organization (ca0-ca8); page length = 512 bits burst length and sequence burst length starting address (a2 a1 a0) sequential addr essing (decimal) interleave addressing (decimal) 2 x x 0 0, 1 0, 1 x x 1 1, 0 1, 0 4 x 0 0 0, 1, 2, 3 0, 1, 2, 3 x 0 1 1, 2, 3, 0 1, 0, 3, 2 x 1 0 2, 3, 0, 1 2, 3, 0, 1 x 1 1 3, 0, 1, 2 3, 2, 1, 0 8 0 0 0 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 0 0 1 1, 2, 3, 4, 5, 6, 7, 0 1, 0, 3, 2, 5, 4, 7, 6 0 1 0 2, 3, 4, 5, 6, 7, 0, 1 2, 3, 0, 1, 6, 7, 4, 5 0 1 1 3, 4, 5, 6, 7, 0, 1, 2 3, 2, 1, 0, 7, 6, 5, 4 1 0 0 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3 1 0 1 5, 6, 7, 0, 1, 2, 3, 4 5, 4, 7, 6, 1, 0, 3, 2 1 1 0 6, 7, 0, 1, 2, 3, 4, 5 6, 7, 4, 5, 2, 3, 0, 1 1 1 1 7, 0, 1, 2, 3, 4, 5, 6 7, 6, 5, 4, 3, 2, 1, 0 256 (full page) n= a0-a7 cn, cn1+2, cn+3, c+4, ... not supported nt5sv8m16fs / nt5sv8m16ft 128mb synchronous dram rev 1.4 08/2009 9 ? nanya technology corporation nanya reserves the right to change products and spe cifications without notice. bank activate command in relation to the operation of a fast page mode dr am, the bank activate command correlates to a falli ng ras signal. the bank activate command is issued by holding cas and we high with cs and ras low at the rising edge of the clock. the bank sele ct address ba0 - ba1 is used to select the desired ban k. the row address a0 - a11 is used to determine wh ich row to activate in the selected bank. the bank activate command must be applied before an y read or write operation can be executed. the dela y from when the bank activate command is applied to when the first read or write operation can begin must meet or exce ed the ras to cas delay time (t rcd ). once a bank has been activated it must be precha rged before another bank activate command can be applied to the same bank. the minimum time interval between successive bank activate commands to the s ame bank is deter- mined by the ras cycle time of the device (t rc ). the minimum time interval between interleaved ba nk activate commands (bank a to bank b and vice versa) is the bank to ba nk delay time (t rrd ). the maximum time that each bank can be held acti ve is specified as t ras(max) . bank select the bank select inputs, ba0 and ba1, determine the bank to be used during a bank activate, precharge, read, or write oper- ation. bank activate command cycle bank selection bits ba0 ba1 bank 0 0 bank 0 1 0 bank 1 0 1 bank 2 1 1 bank 3 address ck t0 t2 t1 t3 tn tn+1 tn+2 tn+3 command nop nop nop nop bank a row addr. bank a activate write a with auto bank a col. addr. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . bank b activate bank a row addr. bank a activate ras -cas delay ( t rcd ) : ?h? or ?l? ras cycle time ( t rc ) precharge ras - ras delay time ( t rrd ) bank b row addr. (cas latency = 3, t rcd = 3) nt5sv8m16fs / nt5sv8m16ft 128mb synchronous dram rev 1.4 08/2009 10 ? nanya technology corporation nanya reserves the right to change products and spe cifications without notice. read and write access modes after a bank has been activated, a read or write cy cle can be executed. this is accomplished by settin g ras high and cas low at the clock?s rising edge after the necessary ras to cas delay (t rcd ). we must also be defined at this time to determine whether the access cycle is a read operation (we high), or a write operation (we low). the address inputs determine the start- ing column address. the sdram provides a wide variety of fast access mo des. a single read or write command will initiate a serial read or write operation on successive clock cycles up to 133 mhz f or pc133 or upto 166mhz for pc166 devices. the numb er of serial data bits for each access is equal to the burst length, which is programmed into the mode register. similar to page mode of conventional drams, a read or write cycle can not begin until the sense amplif iers latch the selected row address information. the refresh period (t ref ) is what limits the number of random column access es to an activated bank. a new burst access can be done even before the prev ious burst ends. the ability to interrupt a burst o peration at every clock cycle is supported; this is referred to as the 1-n rule. when the previous burst is interrupted by ano ther read or write com- mand, the remaining addresses are overridden by the new address. precharging an active bank after each read or write operation is not necessary providing the same row is to be accessed again. to perform a read or write cycle to a different row within an activated bank, the bank must be prechar ged and a new bank acti- vate command must be issued. when more than one ban k is activated, interleaved (ping pong) bank read o r write operations are possible. by using the programmed burst length and alternating the access and precharge operations between multiple banks, fast and seamless data access operation amon g many different pages can be realized. when multip le banks are acti- vated, column to column interleave operation can be done between different pages. finally, read or wri te commands can be issued to the same bank or between active banks on every clock cycle. nt5sv8m16fs / nt5sv8m16ft 128mb synchronous dram rev 1.4 08/2009 11 ? nanya technology corporation nanya reserves the right to change products and spe cifications without notice. burst read command the burst read command is initiated by having cs and cas low while holding ras and we high at the rising edge of the clock. the address inputs determine the starting column ad dress for the burst, the mode register sets the typ e of burst (sequential or interleave) and the burst length (1, 2, 4, 8). the delay from the start of the command to when the dat a from the first cell appears on the outputs is equal to the value of the cas latency that is set in the mode register. read interrupted by a read a burst read may be interrupted before completion o f the burst by another read command, with the only restriction being that the interval that separates the commands must be at least one clock cycle. when the previous burst is interrupted, the remain- ing addresses are overridden by the new address wit h the burst length. the data from the first read co mmand continues to appear on the outputs until the cas latency from the interrupting read command is sati sfied, at this point the data from the interrupting read command appears. burst read operation read interrupted by a read command read a nop nop nop nop nop nop nop dout a 0 cas latency = 2 t ck3 , dqs cas latency = 3 dout a 1 dout a 2 dout a 3 nop ck t0 t2 t1 t3 t4 t5 t6 t7 t8 t ck2 , dqs dout a 0 dout a 1 dout a 2 dout a 3 (burst length = 4, cas latency = 2, 3) command read a read b nop nop nop nop nop nop t ck2 , dqs cas latency = 2 t ck3 , dqs cas latency = 3 nop ck t0 t2 t1 t3 t4 t5 t6 t7 t8 dout b 0 dout b 1 dout b 2 dout b 3 dout a 0 dout b 0 dout b 1 dout b 2 dout b 3 dout a 0 (burst length = 4, cas latency = 2, 3) nt5sv8m16fs / nt5sv8m16ft 128mb synchronous dram rev 1.4 08/2009 12 ? nanya technology corporation nanya reserves the right to change products and spe cifications without notice. read interrupted by a write to interrupt a burst read with a write command, dqm may be needed to place the dqs (output drivers) in a high impedance state to avoid data contention on the dq bus. if a read command will issue data on the first or second clocks cycles of the write operation, dqm is needed to insure the dqs ar e tri-stated. after that point the write command wi ll have control of the dq bus. minimum read to write interval command nop nop read a write a nop nop nop dqm din a 0 din a 1 din a 2 din a 3 : ?h? or ?l? din a 0 din a 1 din a 2 din a 3 t ck2 , dqs cas latency = 2 t ck3 , dqs cas latency = 3 ck t0 t2 t1 t3 t4 t5 t6 t7 t8 nop nop (burst length = 4, cas latency = 2, 3) dqm high for cas latency = 2 only. required to mask first bit of read data. nt5sv8m16fs / nt5sv8m16ft 128mb synchronous dram rev 1.4 08/2009 13 ? nanya technology corporation nanya reserves the right to change products and spe cifications without notice. non-minimum read to write interval command nop nop read a write a nop nop nop dqm din a 0 din a 1 din a 2 din a 3 din a 0 din a 1 din a 2 din a 3 t ck2 , dqs cas latency = 2 t ck3 , dqs cas latency = 3 ck t0 t2 t1 t3 t4 t5 t6 t7 t8 nop nop cl = 3: dqm needed to mask first bit of read data. cl = 2: dqm needed to mask first, second bit of read data. (burst length = 4, cas latency = 2, 3) : dqm high for cas latency = 2 : dqm high for cas latency = 3 nt5sv8m16fs / nt5sv8m16ft 128mb synchronous dram rev 1.4 08/2009 14 ? nanya technology corporation nanya reserves the right to change products and spe cifications without notice. burst write command the burst write command is initiated by having cs , cas , and we low while holding ras high at the rising edge of the clock. the address inputs determine the starting column ad dress. there is no cas latency required for burst write cycles. data for the first burst write cycle must be applied on the dq p ins on the same clock cycle that the write command is issued. the remaining data inputs must be supplied on each subsequent ris ing clock edge until the burst length is completed. when the burst has fin- ished, any additional data supplied to the dq pins will be ignored. write interrupted by a write a burst write may be interrupted before completion of the burst by another write command. when the pre vious burst is inter- rupted, the remaining addresses are overridden by t he new address and data will be written into the de vice until the pro- grammed burst length is satisfied. burst write operation write interrupted by a write command nop write a nop nop nop nop nop nop dqs din a 0 din a 1 din a 2 din a 3 nop ck t0 t2 t1 t3 t4 t5 t6 t7 t8 extra data is masked. the first data element and the write are registered on the same clock edge. ( burst length = 4, cas latency = 2, 3) : ?h? or ?l? command nop write a write b nop nop nop nop nop dqs din a 0 din b 0 din b 1 din b 2 nop din b 3 ck t0 t2 t1 t3 t4 t5 t6 t7 t8 1 ck interval (burst length = 4, cas latency = 2, 3) nt5sv8m16fs / nt5sv8m16ft 128mb synchronous dram rev 1.4 08/2009 15 ? nanya technology corporation nanya reserves the right to change products and spe cifications without notice. write interrupted by a read a read command will interrupt a burst write operati on on the same clock cycle that the read command is registered. the dqs must be in the high impedance state at least one cy cle before the interrupting read data appears on th e outputs to avoid data contention. when the read command is registered, an y residual data from the burst write cycle will be ignored. data that is pre- sented on the dq pins before the read command is in itiated will actually be written to the memory. minimum write to read interval command nop write a read b nop nop nop nop nop nop t ck2 , dqs cas latency = 2 din a 0 t ck3 , dqs cas latency = 3 din a 0 ck t0 t2 t1 t3 t4 t5 t6 t7 t8 input data for the write is masked. input data must be removed from the dqs at least on e clock cycle before the read data appears on the outputs t o avoid data contention. dout b 0 dout b 1 dout b 2 dout b 3 dout b 0 dout b 1 dout b 2 dout b 3 (burst length = 4, cas latency = 2, 3) : ?h? or ?l? nt5sv8m16fs / nt5sv8m16ft 128mb synchronous dram rev 1.4 08/2009 16 ? nanya technology corporation nanya reserves the right to change products and spe cifications without notice. non-minimum write to read interval command write a read b nop nop nop nop nop nop t ck2 , dqs cas latency = 2 din a 0 t ck3 , dqs cas latency = 3 din a 0 ck t0 t2 t1 t3 t4 t5 t6 t7 t8 input data for the write is masked. input data must be removed from the dqs at least on e clock cycle before the read data appears on the outputs t o avoid data contention. dout b 0 dout b 1 dout b 2 dout b 3 dout b 0 dout b 1 dout b 2 dout b 3 nop din a 1 din a 1 (burst length = 4, cas latency = 2, 3) : ?h? or ?l? nt5sv8m16fs / nt5sv8m16ft 128mb synchronous dram rev 1.4 08/2009 17 ? nanya technology corporation nanya reserves the right to change products and spe cifications without notice. auto-precharge operation before a new row in an active bank can be opened, t he active bank must be precharged using either the precharge command or the auto-precharge function. when a read or a wr ite command is given to the sdram, the cas timing accepts one extra address, column address a10, to allow the active ba nk to automatically begin precharge at the earliest possible moment during the burst read or write cycle. if a10 is low when t he read or write command is issued, then normal rea d or write burst opera- tion is executed and the bank remains active at the completion of the burst sequence. if a10 is high w hen the read or write command is issued, then the auto-precharge function is engaged. during auto-precharge, a read command will execute as normal with the exception that the active bank will begin to precharge before all burst read cycles ha ve been completed. regardless of burst length, the precharge will begi n (cas latency - 1) clocks prior to the last data output. auto-precharge can also be implemented during write commands. a read or write command without auto-precharge can be terminated in the midst of a burst operation. ho wever, a read or write command with auto-precharge cannot be interru pted by a command to the same bank. therefore use o f a read, write, or precharge command to the same bank is prohibited du ring a read or write cycle with auto-precharge unti l the entire burst oper- ation is completed. once the precharge operation ha s started the bank cannot be reactivated until the precharge time (t rp ) has been satisfied. when using the auto-precharge command, the interval between the bank activate command and the beginnin g of the internal precharge operation must satisfy t ras(min) . if this interval does not satisfy t ras(min) then t rcd must be extended. burst read with auto-precharge command nop nop nop nop read a auto-precharge t rp ? ck t0 t2 t1 t3 t4 t5 t6 t7 t8 nop nop nop t rp ? * * t ck2 , dqs cas latency = 2 t ck3 , dqs cas latency = 3 begin auto-precharge * bank can be reactivated at completion of t rp . dout a 0 dout a 0 nop ? t rp is a function of clock cycle time and speed sort. see the clock frequency and latency table. (burst length = 1, cas latency = 2, 3) nt5sv8m16fs / nt5sv8m16ft 128mb synchronous dram rev 1.4 08/2009 18 ? nanya technology corporation nanya reserves the right to change products and spe cifications without notice. burst read with auto-precharge burst read with auto-precharge command nop nop nop nop read a auto-precharge t rp ? ck t0 t2 t1 t3 t4 t5 t6 t7 t8 nop nop nop t rp ? * * * t ck2 , dqs cas latency = 2 t ck3 , dqs cas latency = 3 begin auto-precharge dout a 0 dout a 0 nop dout a 1 dout a 1 * bank can be reactivated at completion of t rp . ? t rp is a function of clock cycle time and speed sort. see the clock frequency and latency table. (burst length = 2, cas latency = 2, 3) command nop nop nop nop read a auto-precharge t rp ? ck t0 t2 t1 t3 t4 t5 t6 t7 t8 nop nop nop t rp ? * * * t ck2 , dqs cas latency = 2 t ck3 , dqs cas latency = 3 begin auto-precharge dout a 0 dout a 1 dout a 2 dout a 3 nop dout a 0 dout a 1 dout a 2 dout a 3 * bank can be reactivated at completion of t rp . ? t rp is a function of clock cycle time and speed sort. see the clock frequency and latency table. (burst length = 4, cas latency = 2, 3) nt5sv8m16fs / nt5sv8m16ft 128mb synchronous dram rev 1.4 08/2009 19 ? nanya technology corporation nanya reserves the right to change products and spe cifications without notice. although a read command with auto-precharge can not be interrupted by a command to the same bank, it c an be interrupted by a read or write command to a different bank. if the command is issued before auto-precharge begins then the precharge function will begin with the new command. the bank being auto-precharged may be reactivated after the delay t rp . if interrupting a read command with auto-precharge with a write command, dqm must be used to avoid dq contention. burst read with auto-precharge interrupted by read burst read with auto-precharge interrupted by write t rp ? command nop nop nop nop read a auto-precharge ck t0 t2 t1 t3 t4 t5 t6 t7 t8 nop nop t rp ? t ck2 , dqs cas latency = 2 t ck3 , dqs cas latency = 3 * bank can be reactivated at completion of t rp . dout a 0 dout a 1 nop dout a 0 dout a 1 dout b 0 dout b 1 read b dout b 2 dout b 3 dout b 0 dout b 1 dout b 2 dout b 3 ? t rp is a function of clock cycle time and speed sort. see the clock frequency and latency table. * * (burst length = 4, cas latency = 2, 3) command nop nop nop read a auto-precharge t rp ? ck t0 t2 t1 t3 t4 t5 t6 t7 t8 nop nop t ck2, dqs cas latency = 2 dqm nop dout a 0 din b 0 din b 1 write b din b 2 din b 3 nop din b 4 * bank can be reactivated at completion of t rp . ? t rp is a function of clock cycle time and speed sort. . see the clock frequency and latency table . * (burst length = 8, cas latency = 2) nt5sv8m16fs / nt5sv8m16ft 128mb synchronous dram rev 1.4 08/2009 20 ? nanya technology corporation nanya reserves the right to change products and spe cifications without notice. if a10 is high when a write command is issued, the write with auto-precharge function is initiated. th e bank undergoing auto- precharge cannot be reactivated until t dal , data-in to active delay, is satisfied. similar to the read command, a write command with a uto-precharge can not be interrupted by a command t o the same bank. it can be interrupted by a read or write command to a different bank, however. the interrupting comman d will terminate the write. the bank undergoing auto-precharge can not be reactivated until t dal is satisfied. burst write with auto-precharge burst write with auto-precharge interrupted by writ e din a 0 command nop nop nop nop write a auto-precharge din a 1 ck t0 t2 t1 t3 t4 t5 t6 t7 t8 nop din a 0 din a 1 t ck2 , dqs cas latency = 2 t ck3 , dqs cas latency = 3 nop nop nop * bank can be reactivated at completion of t dal . t dal ? t dal ? * * (burst length = 2, cas latency = 2, 3) see the clock frequency and latency table. ? t dal is a function of clock cycle time and speed sort. din a 0 command nop nop nop write a auto-precharge din a 1 t dal ? ck t0 t1 t2 t3 t4 t5 nop t ck3, dqs cas latency = 3 write b din b 0 din b 1 din b 2 din b 3 t6 t7 t8 nop nop nop * bank can be reactivated at completion of t dal . * (burst length = 4, cas latency = 3) see the clock frequency and latency table. ? t dal is a function of clock cycle time and speed sort. nt5sv8m16fs / nt5sv8m16ft 128mb synchronous dram rev 1.4 08/2009 21 ? nanya technology corporation nanya reserves the right to change products and spe cifications without notice. precharge command the precharge command is used to precharge or close a bank that has been activated. the precharge comm and is triggered when cs , ras , and we are low and cas is high at the rising edge of the clock. the prech arge command can be used to pre- charge each bank separately or all banks simultaneo usly. three address bits, a10, ba0, and ba1, are us ed to define which bank(s) is to be precharged when the command is iss ued. for read cycles, the precharge command may be appli ed (cas latency - 1) prior to the last data output. for wr ite cycles, a delay must be satisfied from the start of the last burst write cycle until the precharge command can b e issued. this delay is known as t dpl , data-in to precharge delay. after the precharge command is issued, the precharg ed bank must be reactivated before a new read or wr ite access can be executed. the delay between the precharge command a nd the activate command must be greater than or equ al to the pre- charge time (t rp ). burst write with auto-precharge interrupted by read bank selection for precharge by address bits a10 bank select precharged bank(s) low ba0, ba1 single bank defined by ba0, ba1 high don?t care all banks din a 0 command nop nop nop write a auto-precharge din a 1 ck t0 t2 t1 t3 t4 t5 t6 t7 t8 nop nop nop * t ck3 , dqs cas latency = 3 bank a can be reactivated at completion of t dal . * read b din a 2 nop dout b 0 dout b 1 dout b 2 t dal ? (burst length = 4, cas latency = 3) see the clock frequency and latency table. ? t dal is a function of clock cycle time and speed sort. nt5sv8m16fs / nt5sv8m16ft 128mb synchronous dram rev 1.4 08/2009 22 ? nanya technology corporation nanya reserves the right to change products and spe cifications without notice. burst read followed by the precharge command burst write followed by the precharge command command read ax 0 nop nop nop nop nop nop nop t ck2 , dqs cas latency = 3 ck t0 t2 t1 t3 t4 t5 t6 t7 t8 dout ax 0 dout ax 1 dout ax 2 dout ax 3 precharge a t rp bank a can be reactivated at completion of t rp . * * (burst length = 4, cas latency = 3) ? ? t rp is a function of clock cycle and speed sort. command nop nop nop write ax 0 ck t0 t2 t1 t3 t4 t5 t6 t7 t8 nop nop nop din ax 0 din ax 1 bank can be reactivated at completion of t rp . * activate bank ax t ck2, dqs cas latency = 2 t dpl ? * t rp ? precharge a ? t dpl and t rp are functions of clock cycle and speed sort. see the clock frequency and latency table. (burst length = 2, cas latency = 2) nt5sv8m16fs / nt5sv8m16ft 128mb synchronous dram rev 1.4 08/2009 23 ? nanya technology corporation nanya reserves the right to change products and spe cifications without notice. precharge termination the precharge command may be used to terminate eith er a burst read or burst write operation. when the precharge command is issued, the burst operation is terminated and ba nk precharge begins. for burst read operations, val id data will continue to appear on the data bus as a function of cas latency. burst read interrupted by precharge command read ax 0 nop nop nop nop nop nop nop t ck2 , dqs cas latency = 2 ck t0 t2 t1 t3 t4 t5 t6 t7 t8 dout ax 0 dout ax 1 dout ax 2 dout ax 3 precharge a t ck3 , dqs cas latency = 3 dout ax 0 dout ax 1 dout ax 2 dout ax 3 t rp ? t rp ? * * bank a can be reactivated at completion of t rp . * see the clock frequency and latency table. (burst length = 8, cas latency = 2, 3) ? t rp is a function of clock cycle time and speed sort. nt5sv8m16fs / nt5sv8m16ft 128mb synchronous dram rev 1.4 08/2009 24 ? nanya technology corporation nanya reserves the right to change products and spe cifications without notice. burst write operations will be terminated by the pr echarge command. the last write data that will be p roperly stored in the device is that write data that is presented to the device a number of clock cycles prior to the precha rge command equal to the data-in to precharge delay, t dpl . precharge termination of a burst write command nop nop nop write ax 0 ck t0 t2 t1 t3 t4 t5 t6 t7 t8 nop nop nop din ax 1 din ax 2 t dpl ? din ax 0 t ck2 , dqs cas latency = 2 nop din ax 1 din ax 2 din ax 0 t ck3 , dqs cas latency = 3 dqm precharge a ? t dpl is an asynchronous timing and may be completed in one or two clock cycles depending on clock cycle time. (burst length = 8, cas latency = 2, 3) t dpl ? nt5sv8m16fs / nt5sv8m16ft 128mb synchronous dram rev 1.4 08/2009 25 ? nanya technology corporation nanya reserves the right to change products and spe cifications without notice. automatic refresh command (cas before ras refresh) when cs , ras , and cas are held low with cke and we high at the rising edge of the clock, the chip ent ers the automatic refresh mode (cbr). all banks of the sdram must be precharged and idle for a minimum of the precharge time (t rp ) before the auto refresh command (cbr) can be applied. an address counter, internal to the device provides th e address during the refresh cycle. no control of the external address p ins is required once this cycle has started. when the refresh cycle has completed, all banks of the sdram will be in the precharged (idle) state. a delay between the auto refresh command (cbr) and the next activate command or subsequent auto refresh command must be greater than or equal to the ras cycle time (t rc ). self refresh command the sdram device has a built-in timer to accommodat e self refresh operation. the self refresh command is defined by hav- ing cs , ras , cas , and cke held low with we high at the rising edge of the clock. all banks mu st be idle prior to issuing the self refresh command. once the command is registere d, cke must be held low to keep the device in self refresh mode. when the sdram has entered self refresh mode all of the external control signals, except cke, are disa bled. the clock is internally disabled during self refresh operation t o save power. the user may halt the external clock while the device is in self refresh mode, however, the clock must be restarted before the device can exit self refresh operation. once the clock is cycling, the device will exit self refresh operatio n after cke is returned high. a minimum delay time is required when the device exits self refresh operation and before the next co mmand can be issued. this delay is equal to the ras cycle time (t rc ) plus the self refresh exit time (t srex ). nt5sv8m16fs / nt5sv8m16ft 128mb synchronous dram rev 1.4 08/2009 26 ? nanya technology corporation nanya reserves the right to change products and spe cifications without notice. power down mode in order to reduce standby power consumption, two p ower down modes are available: precharge and active power down mode. to enter precharge power down mode, all banks must be precharged and the necessary precharge del ay (t rp ) must occur before the sdram can enter the power down mod e. if a bank is activated but not performing a read or write operation, active power down mode will be entered. (issuing a power down mode command when the device is performi ng a read or write operation causes the device to enter clock su spend mode. see the following clock suspend section .) once the power down mode is initiated by holding cke low, all of t he receiver circuits except cke are gated off. the power down mode does not perform any refresh operations, therefore the d evice can?t remain in power down mode longer than t he refresh period (t ref ) of the device. the power down mode is exited by bringing cke high. when cke goes high, a no operation command (or dev ice deselect command) is required on the next rising clock edge. power down mode exit timing command nop command nop nop nop nop nop cke : ?h? or ?l? ck tm tm+2 tm+1 tm+3 tm+4 tm+5 tm+6 tm+7 tm+ 8 t ces(min) t ck nt5sv8m16fs / nt5sv8m16ft 128mb synchronous dram rev 1.4 08/2009 27 ? nanya technology corporation nanya reserves the right to change products and spe cifications without notice. data mask the sdram has a data mask function that can be used in conjunction with data read and write cycles. wh en the data mask is activated (dqm high) during a write cycle, the writ e operation is prohibited immediately (zero clock l atency). if the data mask is activated during a read cycle, the data outputs are disabled and become high impedance after a two-clo ck delay, independent of cas latency. no operation command the no operation command should be used in cases wh en the sdram is in an idle or a wait state. the pur pose of the no operation command is to prevent the sdram from regi stering any unwanted commands between operations. a no operation command is registered when cs is low with ras , cas , and we held high at the rising edge of the clock. a no op eration com- mand will not terminate a previous operation that i s still executing, such as a burst read or write cy cle. deselect command the deselect command performs the same function as a no operation command. deselect command occurs whe n cs is brought high, the ras , cas , and we signals become don?t cares. data mask activated during a read cycle command nop read a nop nop nop nop nop nop nop dqm : ?h? or ?l? a two-clock delay before the dqs become hi-z dqs ck t0 t2 t1 t3 t4 t5 t6 t7 t8 dout a 0 dout a 1 (burst length = 4, cas latency = 2) nt5sv8m16fs / nt5sv8m16ft 128mb synchronous dram rev 1.4 08/2009 28 ? nanya technology corporation nanya reserves the right to change products and spe cifications without notice. clock suspend mode during normal access mode, cke is held high, enabli ng the clock. when cke is registered low while at l east one of the banks is active, clock suspend mode is entered. the clock suspend mode deactivates the internal clock and su spends or ?freezes? any clocked operation that was currently being exec uted. there is a one-clock delay between the regist ration of cke low and the time at which the sdram?s operation suspends. w hile in clock suspend mode, the sdram ignores any n ew commands that are issued. the clock suspend mode is exited b y bringing cke high. there is a one clock cycle del ay from when cke returns high to when clock suspend mode is exited. when the operation of the sdram is suspended during the execution of a burst read operation, the last valid data output onto the dq pins will be actively held valid until clock suspend mode is exited. if clock suspend mode is initiated during a burst w rite operation, the input data is masked and is ign ored until the clock sus- pend mode is exited. clock suspend during a read cycle clock suspend during a write cycle ck t0 t2 t1 t3 t4 t5 t6 t7 t8 command nop read a nop nop nop nop cke dqs dout a 0 dout a 2 dout a 1 : ?h? or ?l? a one clock delay before suspend operation starts a one clock delay to exit the suspend command dout element at the dqs when the suspend operation starts is held valid (burst length = 4, cas latency = 2) ck t0 t2 t1 t3 t4 t5 t6 t7 t8 command nop write a nop nop nop nop cke dqs din a 2 din a 3 : ?h? or ?l? a one clock delay before suspend operation starts a one clock delay to exit the suspend command din is masked during the clock suspend period din a 1 din a 0 (burst length = 4, cas latency = 2) nt5sv8m16fs / nt5sv8m16ft 128mb synchronous dram rev 1.4 08/2009 29 ? nanya technology corporation nanya reserves the right to change products and spe cifications without notice. command truth table (see note 1) function device state cke cs ras cas we dqm ba0, ba1 a10 a11, a9-a0 notes previous cycle current cycle mode register set idle h x l l l l x op code auto (cbr) refresh idle h h l l l h x x x x entry self refresh idle h l l l l h x x x x exit self refresh idle (self- refresh) l h h x x x x x x x l h h h single bank precharge see current state table h x l l h l x bs l x 2 precharge all banks see current state table h x l l h l x x h x bank activate idle h x l l h h x bs row address 2 write active h x l h l l x bs l column 2 write with auto-precharge active h x l h l l x bs h column 2 read active h x l h l h x bs l column 2 read with auto-precharge active h x l h l h x bs h column 2 reserved h x l h h l x x x x no operation any h x l h h h x x x x device deselect any h x h x x x x x x x clock suspend mode entry active h l x x x x x x x x 4 clock suspend mode exit active l h x x x x x x x x data write/output enable active h x x x x x l x x x 5 data mask/output disable active h x x x x x h x x x power down mode entry idle/active h l h x x x x x x x 6, 7 l h h h power down mode exit any (power down) l h h x x x x x x x 6, 7 l h h h 1. all of the sdram operations are defined by states of cs , we , ras , cas , and dqm at the positive rising edge of the clock. ref er to the current state truth table. 2. bank select (ba0, ba1): ba0, ba1 = 0,0 selects bank 0; ba0, ba1 = 1,0 selects bank 1; ba0, ba1 = 0,1 sele cts bank 2; ba0, ba1 = 1,1 selects bank 3. 3. not applicable. 4. during normal access mode, cke is held high and ck i s enabled. when it is low, it freezes the internal clo ck and extends data read and write operations. one clock delay is required for mode entry and exit. 5. the dqm has two functions for the data dq read and write operations. during a read cycle, when dqm goes h igh at a clock timing the data outputs are disabled and become high impedance a fter a two-clock delay. dqm also provides a data mask fun ction for write cycles. when it activates, the write operation at the clock is pr ohibited (zero clock latency). 6. all banks must be precharged before entering the po wer down mode. (if this command is issued during a bu rst operation, the device state will be clock suspend mode.) the power down mod e does not perform any refresh operations; therefore th e device can?t remain in this mode longer than the refresh period (t ref ) of the device. one clock delay is required for mode en try and exit. 7. a no operation or device deselect command is required on the next clock edge following cke going high. nt5sv8m16fs / nt5sv8m16ft 128mb synchronous dram rev 1.4 08/2009 30 ? nanya technology corporation nanya reserves the right to change products and spe cifications without notice. clock enable (cke) truth table current state cke command action notes previous cycle current cycle cs ras cas we ba0, ba1 a11 - a0 self refresh h x x x x x x x invalid 1 l h h x x x x x exit self refresh with device deselect 2 l h l h h h x x exit self refresh with no operation 2 l h l h h l x x illegal 2 l h l h l x x x illegal 2 l h l l x x x x illegal 2 l l x x x x x x maintain self refresh power down h x x x x x x x invalid 1 l h h x x x x x power down mode exit, all banks idle 2 l h l x x x x x illegal 2 l l x x x x x x maintain power down mode all banks idle h h h x x x refer to the idle state section of the current state truth table 3 h h l h x x 3 h h l l h x 3 h h l l l h x x cbr refresh h h l l l l op code mode register set 4 h l h x x x refer to the idle state section of the current state truth table 3 h l l h x x 3 h l l l h x 3 h l l l l h x x entry self refresh 4 h l l l l l op code mode register set l x x x x x x x power down 4 any state other than listed above h h x x x x x x refer to operations in the current state truth table h l x x x x x x begin clock suspend next cycle 5 l h x x x x x x exit clock suspend next cycle l l x x x x x x maintain clock suspend 1. for the given current state cke must be low in the previous cycle. 2. when cke has a low to high transition, the clock and other inputs are re-enabled asynchronously. the minimu m setup time for cke (t ces ) must be satisfied. when exiting power down mode, a nop command (or device deselect command) is required o n the first rising clock after cke goes high (see page 26). 3. the address inputs depend on the command that is issued . see the idle state section of the current state tru th table for more informa- tion. 4. the precharge power down mode, the self refresh mo de, and the mode register set can only be entered from the all banks idle state. 5. must be a legal command as defined in the current state truth table. nt5sv8m16fs / nt5sv8m16ft 128mb synchronous dram rev 1.4 08/2009 31 ? nanya technology corporation nanya reserves the right to change products and spe cifications without notice. current state truth table (part 1 of 3)(see note 1) current state command action notes cs ras cas we ba0,ba1 a11 - a0 description idle l l l l op code mode register set set the mode register 2 l l l h x x auto or self refresh start auto or self refresh 2 , 3 l l h l bs x precharge no operation l l h h bs row address bank activate activate the specified ba nk and row l h l l bs column write w/o precharge illegal 4 l h l h bs column read w/o precharge illegal 4 l h h h x x no operation no operation h x x x x x device deselect no operation or power down 5 row active l l l l op code mode register set illegal l l l h x x auto or self refresh illegal l l h l bs x precharge precharge 6 l l h h bs row address bank activate illegal 4 l h l l bs column write start write; determine if auto pre charge 7, 8 l h l h bs column read start read; determine if auto precha rge 7, 8 l h h h x x no operation no operation h x x x x x device deselect no operation read l l l l op code mode register set illegal l l l h x x auto or self refresh illegal l l h l bs x precharge terminate burst; start the precharge l l h h bs row address bank activate illegal 4 l h l l bs column write terminate burst; start the write cycl e 8, 9 l h l h bs column read terminate burst; start a new read cycl e 8, 9 l h h l x x burst stop burst stop l h h h x x no operation continue the burst h x x x x x device deselect continue the burst write l l l l op code mode register set illegal l l l h x x auto or self refresh illegal l l h l bs x precharge terminate burst; start the precharge l l h h bs row address bank activate illegal 4 l h l l bs column write terminate burst; start a new write cycle 8, 9 l h l h bs column read terminate burst; start the read cycle 8 , 9 l h h l x x burst stop burst stop l h h h x x no operation continue the burst h x x x x x device deselect continue the burst 1. cke is assumed to be active (high) in the previous cycle for all entries. the current state is the state of t he bank that the command is being applied to. 2. all banks must be idle; otherwise, it is an illegal a ction. 3. if cke is active (high) the sdram will start the aut o (cbr) refresh operation, if cke is inactive (low) t han the self refresh mode is entered. 4. the current state refers to only one of the banks. i f bs selects this bank then the action is illegal. if bs selects the bank not being refer- enced by the current state then the action may be legal depending on the state of that bank. 5. if cke is inactive (low) then the power down mode i s entered; otherwise there is a no operation. 6. the minimum and maximum active time (t ras ) must be satisfied. 7. the ras to cas delay (t rcd ) must occur before the command is given. 8. column address a10 is used to determine if the auto precharge function is activated. 9. the command must satisfy any bus contention, bus turn ar ound, and/or write recovery requirements. 10. the command is illegal if the minimum bank to bank delay time (t rrd ) is not satisfied. nt5sv8m16fs / nt5sv8m16ft 128mb synchronous dram rev 1.4 08/2009 32 ? nanya technology corporation nanya reserves the right to change products and spe cifications without notice. read with auto pre- charge l l l l op code mode register set illegal l l l h x x auto or self refresh illegal l l h l bs x precharge illegal 4 l l h h bs row address bank activate illegal 4 l h l l bs column write illegal 4 l h l h bs column read illegal 4 l h h h x x no operation continue the burst h x x x x x device deselect continue the burst write with auto precharge l l l l op code mode register set illegal l l l h x x auto or self refresh illegal l l h l bs x precharge illegal 4 l l h h bs row address bank activate illegal 4 l h l l bs column write illegal 4 l h l h bs column read illegal 4 l h h h x x no operation continue the burst h x x x x x device deselect continue the burst precharging l l l l op code mode register set illegal l l l h x x auto or self refresh illegal l l h l bs x precharge no operation; bank(s) idle after t rp l l h h bs row address bank activate illegal 4 l h l l bs column write illegal 4 l h l h bs column read illegal 4 l h h h x x no operation no operation; bank(s) idle after t rp h x x x x x device deselect no operation; bank(s) idle after t rp row activating l l l l op code mode register set illegal l l l h x x auto or self refresh illegal l l h l bs x precharge illegal 4 l l h h bs row address bank activate illegal 4, 10 l h l l bs column write illegal 4 l h l h bs column read illegal 4 l h h h x x no operation no operation; row active after t rcd h x x x x x device deselect no operation; row active after t rcd current state truth table (part 2 of 3)(see note 1) current state command action notes cs ras cas we ba0,ba1 a11 - a0 description 1. cke is assumed to be active (high) in the previous cycle for all entries. the current state is the state of t he bank that the command is being applied to. 2. all banks must be idle; otherwise, it is an illegal a ction. 3. if cke is active (high) the sdram will start the aut o (cbr) refresh operation, if cke is inactive (low) t han the self refresh mode is entered. 4. the current state refers to only one of the banks. i f bs selects this bank then the action is illegal. if bs selects the bank not being refer- enced by the current state then the action may be legal depending on the state of that bank. 5. if cke is inactive (low) then the power down mode i s entered; otherwise there is a no operation. 6. the minimum and maximum active time (t ras ) must be satisfied. 7. the ras to cas delay (t rcd ) must occur before the command is given. 8. column address a10 is used to determine if the auto precharge function is activated. 9. the command must satisfy any bus contention, bus turn ar ound, and/or write recovery requirements. 10. the command is illegal if the minimum bank to bank delay time (t rrd ) is not satisfied. nt5sv8m16fs / nt5sv8m16ft 128mb synchronous dram rev 1.4 08/2009 33 ? nanya technology corporation nanya reserves the right to change products and spe cifications without notice. write recovering l l l l op code mode register set illegal l l l h x x auto or self refresh illegal l l h l bs x precharge illegal 4 l l h h bs row address bank activate illegal 4 l h l l bs column write start write; determine if auto pre charge 9 l h l h bs column read start read; determine if auto precha rge 9 l h h h x x no operation no operation; row active after t dpl h x x x x x device deselect no operation; row active after t dpl write recovering with auto pre- charge l l l l op code mode register set illegal l l l h x x auto or self refresh illegal l l h l bs x precharge illegal 4 l l h h bs row address bank activate illegal 4 l h l l bs column write illegal 4, 9 l h l h bs column read illegal 4, 9 l h h h x x no operation no operation; precharge after t dpl h x x x x x device deselect no operation; precharge after t dpl refreshing l l l l op code mode register set illegal l l l h x x auto or self refresh illegal l l h l bs x precharge illegal l l h h bs row address bank activate illegal l h l l bs column write illegal l h l h bs column read illegal l h h h x x no operation no operation; idle after t rc h x x x x x device deselect no operation; idle after t rc mode register accessing l l l l op code mode register set illegal l l l h x x auto or self refresh illegal l l h l bs x precharge illegal l l h h bs row address bank activate illegal l h l l bs column write illegal l h l h bs column read illegal l h h h x x no operation no operation; idle after two clock cycles h x x x x x device deselect no operation; idle after two cl ock cycles current state truth table (part 3 of 3)(see note 1) current state command action notes cs ras cas we ba0,ba1 a11 - a0 description 1. cke is assumed to be active (high) in the previous cycle for all entries. the current state is the state of t he bank that the command is being applied to. 2. all banks must be idle; otherwise, it is an illegal a ction. 3. if cke is active (high) the sdram will start the aut o (cbr) refresh operation, if cke is inactive (low) t han the self refresh mode is entered. 4. the current state refers to only one of the banks. i f bs selects this bank then the action is illegal. if bs selects the bank not being refer- enced by the current state then the action may be legal depending on the state of that bank. 5. if cke is inactive (low) then the power down mode i s entered; otherwise there is a no operation. 6. the minimum and maximum active time (t ras ) must be satisfied. 7. the ras to cas delay (t rcd ) must occur before the command is given. 8. column address a10 is used to determine if the auto precharge function is activated. 9. the command must satisfy any bus contention, bus turn ar ound, and/or write recovery requirements. 10. the command is illegal if the minimum bank to bank delay time (t rrd ) is not satisfied. nt5sv8m16fs / nt5sv8m16ft 128mb synchronous dram rev 1.4 08/2009 34 ? nanya technology corporation nanya reserves the right to change products and spe cifications without notice. absolute maximum ratings symbol parameter rating units notes v dd power supply voltage -1.0 to +4.6 v 1 v ddq power supply voltage for output -1.0 to +4.6 v 1 v in input voltage -0.3 to v dd +0.3 v 1 v out output voltage -0.3 to v dd +0.3 v 1 t a operating temperature (ambient) commerical 0 to +70 c 1 industrial -40 to +85 c 1 t stg storage temperature -55 to +150 c 1 p d power dissipation 1.0 w 1 i out short circuit output current 50 ma 1 1. stresses greater than those listed under ?absolute ma ximum ratings? may cause permanent damage to the devic e. this is a stress rating only and functional operation of the device at these or any other conditions above those ind icated in the operational sections of this specification is not implied . exposure to absolute maximum rating conditions for exte nded periods may affect reliability. recommended dc operating conditions symbol parameter rating units notes min. typ. max. v dd supply voltage 3.0 3.3 3.6 v 1 v ddq supply voltage for output 3.0 3.3 3.6 v 1 v ih input high voltage 2.0 3.0 v dd + 0.3 v 1, 2 v il input low voltage -0.3 0 0.8 v 1, 3 v oh output logic high voltage 2.4 ? ? v i oh = -2 ma v ol output logic low voltage ? ? 0.4 v i ol = 2 ma 1. all voltages referenced to v ss and v ssq . 2. v ih (max) = v dd + 2.3v for pulse width 3ns. 3. v il (min) = v ss - 2.0v for pulse width 3ns. capacitance (t a = 23 c, f = 1mhz, v dd = 3.3v, v ref =1.4+/-200mv ) symbol parameter min. 64mb max. 128mb max. units c in input capacitance (a0-a11, bs0, bs1, cs , ras , cas , we , cke, dqm) 2.5 5.0 3.8 pf c add address 2.5 5.0 3.8 pf c clk input clock (clk) 2.5 4.0 3.5 pf c out output capacitance (dq0 - dq15) 4.0 6.5 6.0 pf nt5sv8m16fs / nt5sv8m16ft 128mb synchronous dram rev 1.4 08/2009 35 ? nanya technology corporation nanya reserves the right to change products and spe cifications without notice. dc electrical characteristics (v dd = 3.3v 0.3v) symbol parameter min. max. units i i(l) input leakage current, any input (0.0v v in v dd ), all other pins not under test = 0v -1 +1 a i o(l) output leakage current (d out is disabled, 0.0v v out v ddq ) -1 +1 a v oh output level (lvttl) output ?h? level voltage ( iout = -2.0ma) 2.4 ? v v ol output level (lvttl) output ?l? level voltage (i out = +2.0ma) ? 0.4 v dc output load circuit output 1200 50pf 3.3 v 870 v oh (dc) = 2.4v, i oh = -2ma v ol (dc) = 0.4v, i ol = 2ma nt5sv8m16fs / nt5sv8m16ft 128mb synchronous dram rev 1.4 08/2009 36 ? nanya technology corporation nanya reserves the right to change products and spe cifications without notice. dc operating, standby, and refresh currents parameter symbol test condition max. units notes 6k 6ki 75b 75bi operating current i cc1 1 bank operation t rc = t rc (min), t ck = min active-precharge command cycling without burst operation 130 130 90 90 ma 1, 2, 3 precharge standby current in power down mode i cc2p cke v il (max), t ck = min, cs = v ih (min) 4 4 4 4 ma 1 i cc2ps cke v il (max), t ck = infinity, cs = v ih (min) 4 4 4 4 ma 1 precharge standby current in non-power down mode i cc2n cke v ih (min), t ck = min, cs = v ih (min) 20 20 20 20 ma 1, 5 i cc2ns cke v ih (min), t ck = infinity, 10 10 10 10 ma 1, 7 no operating current (active state: 4 bank) i cc3n cke v ih (min), t ck = min, cs = v ih (min) 35 35 35 35 ma 1, 5 i cc3p cke v il (max), t ck = min, 5 7 5 7 ma 1, 6 operating current (burst mode) i cc4 t ck = min, read/ write command cycling, multiple banks active, gapless data, bl = 4 150 150 110 110 ma 1, 3, 4 auto (cbr) refresh current i cc5 t ck = min, t rc = t rc (min) cbr command cycling 220 220 200 200 ma 1 self refresh current i cc6 cke 0.2v 4 4 4 4 ma 1 1. currents given are valid for a single device. . 2. these parameters depend on the cycle rate and are me asured with the cycle determined by the minimum value of t ck and t rc . input signals are changed up to three times during t rc (min). 3. the specified values are obtained with the output open. 4. input signals are changed once during t ck (min). 5. input signals are changed once during three clock cycles. 6. active standby current will be higher if clock suspen d is entered during a burst read cycle (add 1ma per dq ). 7. input signals are stable. nt5sv8m16fs / nt5sv8m16ft 128mb synchronous dram rev 1.4 08/2009 37 ? nanya technology corporation nanya reserves the right to change products and spe cifications without notice. ac characteristics (v dd = 3.3v 0.3v) 1. an initial pause of 200 s, with dqm and cke held high, is required after po wer-up. a precharge all banks command must be given followed by a minimum of two auto (cbr) re fresh cycles before or after the mode register set operation. 2. the transition time is measured between v ih and v il (or between v il and v ih ) 3. in addition to meeting the transition rate specif ication, the clock and cke must transit between v ih and v il (or between v il and v ih ) in a monotonic manner. 4. load circuit a: ac timing tests have v il = 0.4 v and v ih = 2.4 v with the timing referenced to the 1.40v cr ossover point 5. load circuit a: ac measurements assume t t = 1.0ns. ac characteristics diagrams output input clock t oh t setup t hold t ac t lz 1.4v 1.4v 1.4v t t vtt = 1.4v output 50 50pf z o = 50 ac output load circuit (a) t ckh t ckl v il v ih nt5sv8m16fs / nt5sv8m16ft 128mb synchronous dram rev 1.4 08/2009 38 ? nanya technology corporation nanya reserves the right to change products and spe cifications without notice. clock and clock enable parameters symbol parameter -6k/6ki -75b/75bi units notes min. max. min. max. t ck3 clock cycle time, cas latency = 3 6 ? 7.5 ? ns t ck2 clock cycle time, cas latency = 2 10 ? 10 ? ns t ac3 (a) clock access time, cas latency = 3 ? 5 ? 5.4 ns 1 t ac2 (a) clock access time, cas latency = 2 ? 6 ? 6 ns 1 t ckh clock high pulse width 2.5 ? 2.5 ? ns t ckl clock low pulse width 2.5 ? 2.5 ? ns t ces clock enable set-up time 1.5 ? 1.5 ? ns t ceh clock enable hold time 1.0 ? 0.8 ? ns t sb power down mode entry time 0 6 0 7.5 ns t t transition time (rise and fall) 0.3 8 0.5 10 ns 1. access time is measured at 1.4v. see ac characteristics : notes 1, 2, 3, 4, 5 and load circuit a. common parameters symbol parameter -6k/6ki -75b/75bi units notes min. max. min. max. t cs command setup time 1.5 ? 1.5 ? ns t ch command hold time 0.8 ? 0.8 ? ns t as address and bank select set-up time 1.5 ? 1.5 ? ns t ah address and bank select hold time 0.8 ? 0.8 ? ns t rcd ras to cas delay 18 ? 20 ? ns 1 t rc bank cycle time 60 ? 67.5 ? ns 1 t ras active command period 42 100k 45 100k ns 1 t rp precharge time 18 ? 20 ? ns 1 t rrd bank to bank delay time 12 ? 15 ? ns 1 t ccd cas to cas delay time 1 ? 1 ? ck 1. these parameters account for the number of clock cycle a nd depend on the operating frequency of the clock, as follows: the number of clock cycles = specified value of timing / clock period (count fractions as a whole number). mode register set cycle symbol parameter -6k/6ki -75b/75bi units min. max. min. max. t rsc mode register set cycle time 12 ? 15 ? ns nt5sv8m16fs / nt5sv8m16ft 128mb synchronous dram rev 1.4 08/2009 39 ? nanya technology corporation nanya reserves the right to change products and spe cifications without notice. read cycle symbol parameter -6k/6ki -75b/75bi units notes min. max. min. max. t oh data out hold time ? ? ? ? ns 1 2.5 ? 2.7 ? ns 2, 4 t lz data out to low impedance time 0 ? 0 ? ns t hz data out to high impedance time 3 6 3 7 ns 3 t dqz dqm data out disable latency 2 ? 2 ? ck 1. ac output load circuit a. 2. ac output load circuit b. 3. referenced to the time at which the output achieve s the open circuit condition, not to output voltage level s. 4. data out hold time with no load must meet 1.8ns (- 75h, -75d, -75a). refresh cycle symbol parameter -6k/6ki -75b/75bi units notes min. max. min. max. t ref refresh period ? 64 ? 64 ms 1 t srex self refresh exit time 1 ? 1 ? ck 1. 4096 auto refresh cycles. write cycle symbol parameter -6k/6ki -75b/75bi units min. max. min. max. t ds data in set-up time 1.5 ? 1.5 ? ns t dh data in hold time 1 ? 0.8 ? ns t dpl data input to precharge 12 ? 15 ? ns t wr write recovery time 12 ? 15 ? ns t dal3 data in to active delay, cas latency = 3 5 ? 5 ? ck t dal2 data in to active delay, cas latency = 2 4 ? 4 ? ck t dqw dqm write mask latency 0 ? 0 ? ck nt5sv8m16fs / nt5sv8m16ft 128mb synchronous dram rev 1.4 08/2009 40 ? nanya technology corporation nanya reserves the right to change products and spe cifications without notice. clock frequency and latency symbol parameter -6k/6ki -75b/75bi units f ck clock frequency 166 133 mhz t ck clock cycle time 6.0 7.5 ns t aa cas latency 3 3 ck t rp precharge time 3 3 ck t rcd ras to cas delay 3 3 ck t rc bank cycle time 10 9 ck t ras minimum bank active time 7 6 ck t dpl data in to precharge 2 2 ck t dal data in to active/refresh 5 5 ck t rrd bank to bank delay time 2 2 ck t ccd cas to cas delay time 1 1 ck t wl write latency 0 0 ck t dqw dqm write mask latency 0 0 ck t dqz dqm data disable latency 2 2 ck t csl clock suspend latency 1 1 ck nt5sv8m16fs / nt5sv8m16ft 128mb synchronous dram rev 1.4 08/2009 41 ? nanya technology corporation nanya reserves the right to change products and spe cifications without notice. ac parameters for write timing \ ck cke cs dq ras cas we * ba1 dqm t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z a10 a0-a9, t ces t cs t ch t as t rcd t dal ? t ds activate command bank 0 write with auto precharge command bank 0 activate command bank 1 write with auto precharge command bank 1 activate command bank 0 write command bank 0 precharge command bank 0 activate command bank 0 t dh ax0 ax3 ax2 ax1 bx0 bx3 bx2 bx1 ay0 ay3 ay2 ay1 t ck2 t ckh t ckl activate command bank 1 ray cbx cay ray rbx rbx cax rby rby raz raz rax rax t ah * ba0 = ?l? bank2,3 = idle t rc t ceh t dpl ? t rp t rrd t dpl and t dal depend on clock cycle time and (burst length = 4, cas latency = 2) ? speed sort. see the clock frequency and latency table. a11 nt5sv8m16fs / nt5sv8m16ft 128mb synchronous dram rev 1.4 08/2009 42 ? nanya technology corporation nanya reserves the right to change products and spe cifications without notice. ac parameters for read timing (3/3/3) \ ck cke cs dq ras cas we * ba1 dqm t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t10 hi-z a10 a0-a9, t rcd t ras activate command bank 0 activate command bank 1 activate command bank 0 t ck3 read with auto precharge command bank 1 t rc t ac3 t oh bx0 bx1 cbx ray rbx rbx ray cax rax rax * ba0 = ?l? read with auto precharge command bank 0 begin auto precharge bank 0 bank2,3 = idle t rp bx2 begin auto precharge bank 1 t rrd ax3 ax2 ax1 ax0 (burst length = 4, cas latency = 3; t rcd , t rp = 3) a11 nt5sv8m16fs / nt5sv8m16ft 128mb synchronous dram rev 1.4 08/2009 43 ? nanya technology corporation nanya reserves the right to change products and spe cifications without notice. ac parameters for read timing (2/2/2) \ ck cke cs dq ras cas we * ba1 dqm t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t10 hi-z a10 t cs t ch t ceh t as t ah t rrd t rcd t ras(min) t lz activate command bank 0 activate command bank 1 activate command bank 0 t ces t ck2 read with auto precharge command bank 1 t rc t rp t ac2 t oh t hz t ckh bx0 begin auto precharge bank 1 bx1 t hz cbx ray rbx rbx ray cax rax rax t ckl ax0 ax1 * ba0 = ?l? read with auto precharge command bank 0 begin auto precharge bank 0 bank2,3 = idle t rp note: must satisfy t ras(min) for -260: extend t rcd 1 clock (burst length = 2, cas latency = 2; t rcd , t rp = 2) a0-a9, a11 nt5sv8m16fs / nt5sv8m16ft 128mb synchronous dram rev 1.4 08/2009 44 ? nanya technology corporation nanya reserves the right to change products and spe cifications without notice. ac parameters for read timing (3/2/2) \ ck cke cs dq ras cas we * ba1 dqm t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t10 hi-z a10 t cs t ch t ceh t as t ah t rcd t lz activate command bank 0 activate command bank 1 activate command bank 0 t ck3 read with auto precharge command bank 1 t rp t ac3 t oh t hz t ckh bx0 begin auto precharge bank 1 bx1 t hz cbx ray rbx rbx ray cax rax rax t ckl ax0 ax1 * ba0=? l? read with auto precharge command bank 0 begin auto precharge bank 0 bank2,3=idle t rp t ces note: must satisfy t ras(min). extended t rcd 1 clock. not required for bl 4. t rrd t ras t rc (burst length = 2, cas latency = 3; t rcd , t rp = 2) a0-a9, a11 nt5sv8m16fs / nt5sv8m16ft 128mb synchronous dram rev 1.4 08/2009 45 ? nanya technology corporation nanya reserves the right to change products and spe cifications without notice. ac parameters for read timing (3/3/3) \ ck cke cs dq ras cas we * ba1 dqm t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t10 hi-z a10 a0-a9, t rrd t rcd t ras (min) activate command bank 0 activate command bank 1 activate command bank 0 t ck3 read with auto precharge command bank 1 t rc t rp t ac3 t oh bx0 begin auto precharge bank 1 bx1 cbx ray rbx rbx ray cax rax rax read with auto precharge command bank 0 begin auto precharge bank 0 t rp ax0 ax1 note: must satisfy t ras (min). extended t rcd not required for bl 4. t ceh a11 t14 * ba0=? l? bank 2,3=idle (burst length = 2, cas latency = 3; t rcd , t rp = 3) nt5sv8m16fs / nt5sv8m16ft 128mb synchronous dram rev 1.4 08/2009 46 ? nanya technology corporation nanya reserves the right to change products and spe cifications without notice. mode register set \ ck cke cs dq ras cas we ba0,ba1 dqm t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z a10,a11 a0-a9 precharge command all banks mode register set command any command address key t rp t ck2 t rsc (cas latency = 2) nt5sv8m16fs / nt5sv8m16ft 128mb synchronous dram rev 1.4 08/2009 47 ? nanya technology corporation nanya reserves the right to change products and spe cifications without notice. power-on sequence and auto refresh (cbr) \ ck cke cs dq ras cas we bs dqm t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z a10 a0-a9, precharge command all banks t rp minimum of 8 refresh cycles are required 1st auto refresh command t rc high level is required 8th auto refresh command inputs must be stable for 200 s t ck any command 2 clock min. mode register address key set command a11 nt5sv8m16fs / nt5sv8m16ft 128mb synchronous dram rev 1.4 08/2009 48 ? nanya technology corporation nanya reserves the right to change products and spe cifications without notice. clock suspension / dqm during burst read \ ck cke cs dq ras cas we dqm t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z a10 a0-a9, rax ax0 ax1 ax2 ax3 activate command bank 0 clock suspend 2 cycles clock suspend 1 cycle clock suspend 3 cycles rax read command bank 0 cax t hz t ck3 * ba1 ax4 ax6 ax7 t ces t ceh * ba0=? l? bank2,3=idle (burst length = 8, cas latency = 3; t rcd = 3) a11 nt5sv8m16fs / nt5sv8m16ft 128mb synchronous dram rev 1.4 08/2009 49 ? nanya technology corporation nanya reserves the right to change products and spe cifications without notice. clock suspension / dqm during burst write \ ck cke cs dq ras cas we * ba1 dqm t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z a10 a0-a9, rax activate command bank 0 rax cax dax0 clock suspend 1 cycle dax1 dax2 clock suspend 2 cycles clock suspend 3 cycles write command bank 0 t ck3 dax5 dax6 dax7 dax3 * ba0=? l? bank2,3=idle (burst length = 8, cas latency = 3; t rcd = 3) a11 nt5sv8m16fs / nt5sv8m16ft 128mb synchronous dram rev 1.4 08/2009 50 ? nanya technology corporation nanya reserves the right to change products and spe cifications without notice. power down mode and clock suspend \ ck cke cs dq ras cas we * ba1 dqm t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z a10 a0 -a9, t ces t ces valid cax rax rax ax2 ax0 ax1 ax3 activate command bank 0 nop read command bank 0 active standby clock suspension start clock suspension end precharge command bank 0 precharge standby t hz any command t ck2 t ces t sb nop * ba0=? l? bank2,3=idle t sb (burst length = 4, cas latency = 2) a11 nt5sv8m16fs / nt5sv8m16ft 128mb synchronous dram rev 1.4 08/2009 51 ? nanya technology corporation nanya reserves the right to change products and spe cifications without notice. auto refresh (cbr) \ ck cke cs dq ras cas we bs dqm t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z a10 a0-a9, precharge command auto refresh command auto refresh command t rc t rp t rc t ck2 all banks (cas latency = 2) a11 nt5sv8m16fs / nt5sv8m16ft 128mb synchronous dram rev 1.4 08/2009 52 ? nanya technology corporation nanya reserves the right to change products and spe cifications without notice. self refresh (entry and exit) \ ck cke cs dq ras cas we bs dqm t2 t3 t4 t0 t1 hi-z a10 all banks must be idle self refresh entry a0-a9, tm tm+2 tm+3 tm+4 tm+5 tm+1 tm+7 tm+8 tm+9 tm+10 tm+6 tm+13 tm+11 tm+12 tm+15 tm+14 t ces t sb any command t ces t rc t srex self refresh exit power down entry power down exit (note: the ck signal must be reestablished prior to cke returning high.) a11 nt5sv8m16fs / nt5sv8m16ft 128mb synchronous dram rev 1.4 08/2009 53 ? nanya technology corporation nanya reserves the right to change products and spe cifications without notice. random row read (interleaving banks) with precharge \ ck cke cs dq ras cas we * ba1 dqm t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z a10 a0-a9, cby read command bank 1 by0 t ck3 high t ac3 activate command bank 1 rbx rbx activate command bank 0 rax rax cbx read command bank 1 activate command bank 1 rby rby t rcd precharge command bank 1 cax read command bank 0 bx0 bx1 bx2 bx3 bx4 bx5 bx6 ax0 ax1 ax4 ax5 ax6 ax7 precharge command bank 0 * ba0=? l? bank2,3=idle (burst length = 8, cas latency = 3; t rcd , t rp = 3) a11 nt5sv8m16fs / nt5sv8m16ft 128mb synchronous dram rev 1.4 08/2009 54 ? nanya technology corporation nanya reserves the right to change products and spe cifications without notice. random row read (interleaving banks) with auto-prec harge \ ck cke cs dq ras cas we * ba1 dqm t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z a10 a0-a9, cby by0 t ck3 high t ac3 activate command bank 1 rbx rbx activate command bank 0 rax rax cbx activate command bank 1 rby rby t rcd cax bx0 bx1 bx2 bx3 bx4 bx5 bx6 bx7 ax0 ax4 ax5 ax6 read with auto precharge command bank 1 ax1 start auto precharge bank 1 read with auto precharge command bank 0 start auto precharge bank 0 read with auto precharge command bank 1 * ba0=? l? bank2,3=idle rax rax ax7 (burst length = 8, cas latency = 3; t rcd , t rp = 3) a11 nt5sv8m16fs / nt5sv8m16ft 128mb synchronous dram rev 1.4 08/2009 55 ? nanya technology corporation nanya reserves the right to change products and spe cifications without notice. random row write (interleaving banks) with auto-pre charge \ ck cke cs dq ras cas we * ba1 dqm t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z a10 a0-a9, t ck3 high dax0 dax1 dax4 dax7 dax6 dax5 dbx0 dbx3 dbx2 dbx1 dbx4 dbx5 day2 day1 day0 cax activate command bank 0 rax rax activate command bank 1 rbx rbx activate command bank 0 ray ray cbx cay t rcd dbx7 dbx6 write with auto precharge command bank 0 write with auto precharge command bank 1 write with auto precharge command bank 0 * ba0=? l? bank2,3=idle t dal ? t dal ? ? number of clocks depends on clock cycle time and speed sort. see the clock frequency and latency table. bank may be reactivated at the completion of t dal . (burst length = 8, cas latency = 3; t rcd , t rp = 3) a11 nt5sv8m16fs / nt5sv8m16ft 128mb synchronous dram rev 1.4 08/2009 56 ? nanya technology corporation nanya reserves the right to change products and spe cifications without notice. random row write (interleaving banks) with precharg e \ ck cke cs dq ras cas we * ba1 dqm t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z a10 a0-a9, t ck3 high dax0 dax1 dax4 dax7 dax6 dax5 dbx0 dbx3 dbx2 dbx1 dbx4 dbx5 day2 day1 day0 write command bank 0 cax activate command bank 0 rax rax activate command bank 1 rbx rbx activate command bank 0 ray ray cbx write command bank 1 precharge command bank 0 write command bank 0 cay precharge command bank 1 t rp t rcd dbx7 dbx6 * ba0=? l? bank2,3=idle (burst length = 8, cas latency = 3; t rcd , t rp = 3) t dpl a11 nt5sv8m16fs / nt5sv8m16ft 128mb synchronous dram rev 1.4 08/2009 57 ? nanya technology corporation nanya reserves the right to change products and spe cifications without notice. read / write cycle \ ck cke cs dq ras cas we * ba1 dqm t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z a10 a0-a9, t ck3 write command bank 0 cay day0 day1 day3 ax0 ax1 ax3 ax2 the write data is masked with a zero clock latency the read data is masked with a two clock latency activate command bank0 rax rax cax read command bank 0 day4 precharge command bank 0 * ba0=? l? bank2,3=idle (burst length = 8, cas latency = 3; t rcd , t rp = 3) a11 nt5sv8m16fs / nt5sv8m16ft 128mb synchronous dram rev 1.4 08/2009 58 ? nanya technology corporation nanya reserves the right to change products and spe cifications without notice. interleaved column read cycle \ ck cke cs dq ras cas we * ba1 dqm t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z a10 a0-a9, t ck3 t rcd t ac3 cby read command bank 1 cbz read command bank 1 cay precharge command bank 1 ax0 ax3 ax2 ax1 bx0 by1 by0 bx1 bz0 bz1 ay0 ay3 ay2 ay1 activate command bank 0 rax rax cbx read command bank 1 cax activate command bank 1 read command bank 0 rbx rbx read with auto precharge command bank 0 start auto precharge bank 0 * ba0=? l? bank2,3=idle (burst length = 4, cas latency = 3; t rcd , t rp = 3) a11 nt5sv8m16fs / nt5sv8m16ft 128mb synchronous dram rev 1.4 08/2009 59 ? nanya technology corporation nanya reserves the right to change products and spe cifications without notice. auto precharge after read burst \ ck cke cs dq ras cas we * ba1 dqm t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z a10 a0-a9, t ck3 high read with auto precharge command bank 1 cby start auto precharge bank 1 start auto precharge bank 0 ax3 ax2 ax0 ax1 bx3 bx2 bx0 bx1 ay3 ay2 ay0 ay1 activate command bank 0 rax rax read with auto precharge command bank 1 cbx read with auto precharge command bank 0 activate command bank 1 rbx cax rbx activate command bank 1 read command bank 0 rby cay rby by0 by1 * ba0=? l? bank2,3=idle start bank 1 auto precharge (burst length = 4, cas latency = 3; t rcd , t rp = 3) a11 nt5sv8m16fs / nt5sv8m16ft 128mb synchronous dram rev 1.4 08/2009 60 ? nanya technology corporation nanya reserves the right to change products and spe cifications without notice. auto precharge after write burst \ ck cke cs dq ras cas we * ba1 dqm t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z a10 a0-a9, t ck2 high write with auto precharge command bank 1 cby activate command bank 1 rbx rbx write with auto precharge command bank 1 cbx dax3 dax2 dax1 dax0 dbx3 dbx2 dbx1 dbx0 day3 day2 day1 day0 dby3 dby2 dby1 dby0 daz3 daz2 daz1 daz0 activate command bank 0 raz raz write command bank 0 cax write with auto precharge command bank 0 cay activate command bank 1 rby rby activate command bank 0 rax rax write with auto precharge command bank 0 caz * ba0=? l? bank2,3=idle a11 t dal ? t dal ? ? number of clocks depends on clock cycle and speed s ort. see the clock frequency and latency table. bank may be reactivated at the completion of t dal . t dal ? (burst length = 4, cas latency = 2) nt5sv8m16fs / nt5sv8m16ft 128mb synchronous dram rev 1.4 08/2009 61 ? nanya technology corporation nanya reserves the right to change products and spe cifications without notice. burst read and single write operation \ ck cke cs dq 0 - dq 7 ras cas we * ba1 ldqm a10 a0-a9, dq 8 - dq 15 udqm t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z t ck2 activate command bank 0 rav rav cav read command bank 0 single write command bank 0 caw high cay read command bank 0 av0 daw0 hi-z av2 av1 av3 dax0 av2 av1 ay2 daw0 ay0 ay3 av0 av3 single write command bank 0 ay3 single write command bank 0 daz0 daz0 cax caz lower byte is masked ay0 ay1 upper byte is masked lower byte is masked * ba0=? l? bank2,3=idle (burst length = 4, cas latency = 2) a11 nt5sv8m16fs / nt5sv8m16ft 128mb synchronous dram rev 1.4 08/2009 62 ? nanya technology corporation nanya reserves the right to change products and spe cifications without notice. cs function (only cs signal needs to be asserted at minimum rate) \ ck cke cs dq ras cas we ba0,ba1 dqm t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z a10 a0-a9, a11 t ck3 rax low rax cax cay read command bank a write command bank a activate command bank a precharge command bank a ax0 day0 day3 day2 day1 ax3 ax2 ax1 t rcd t dpl (at 100mhz burst length = 4, cas latency = 3, t rcd , t rp = 3) nt5sv8m16fs / nt5sv8m16ft 128mb synchronous dram rev 1.4 08/2009 63 ? nanya technology corporation nanya reserves the right to change products and spe cifications without notice. package dimensions (400mil; 54 lead; thin small outline package) lead #1 0.80 basic 0.35 10.16 0.13 22.22 0.13 11.76 0.20 - 0.05 + 0.10 0.71ref detail a 0.10 seating plane detail a 0.5 0.1 0.05 min 1.20 max 0.25 basic gage plane nt5sv8m16fs / nt5sv8m16ft 128mb synchronous dram rev 1.4 08/2009 64 ? nanya technology corporation nanya reserves the right to change products and spe cifications without notice. revision log rev date modification 1.0 sep 2006 official release 1.1 jan 2007 add waveforms 1.2 oct 2007 add icc data max description 1.3 sep 2008 add burst stop command in state truth table support industrial temperature scope 1.4 aug 2009 removed cl2 information. nt5sv8m16fs / nt5sv8m16ft 128mb synchronous dram rev 1.4 08/2009 65 ? nanya technology corporation nanya reserves the right to change products and spe cifications without notice. nanya technology corporation. all rights reserved. printed in taiwan, r.o.c. the following are trademarks of nanya technology co rporation in r.o.c, or other countries, or both. nanya nanya logo other company, product and service names may be tra demarks or service marks of others. nanya technology corporation (ntc) reserves the rig ht to make changes without notice. ntc warrants per formance of its semiconductor products and related software to the specifications applicable at the time of sal e in accordance with ntc?s standard warranty. testing and other quality contro l techniques are utilize to the extent ntc deems ne cessary to support this warranty. specific testing of all parameters of eac h device is not necessarily performed, except those mandated by government requirements. certain applications using semiconductor products m ay involve potential risks of death, personal injur y, or severe property or environmental damage (?critical applications?). ntc semiconductor products are not designed, intend , authorized, or warranted to be suitable for use in life-support applications, devices or sy stems or other critical applications. inclusion of ntc products in such applications is u nderstood to be fully at the risk of the customer. use of ntc products in such applications requires the written approval of an ap propriate ntc officer. question concerning potentia l risk applications should be directed to ntc through a local sales office. in order to minimize risks associated with the cust omer?s applications, adequate design and operating safeguards should be provided by customer to minimize the inherent or pr ocedural hazards. ntc assumes no liability of applications assistance , customer product design, software performance, or infringement of patents or services described herein. nor does ntc warrant or represent that any license, either express or im plied, is granted under any patent right, copyright, mask work right, or ot her intellectual property right of ntc covering or relating to any combination, machine, or process in which such semiconductor pro ducts or services might be or are used. nanya technology corporation hwa ya technology park 669, fu hsing 3rd rd., kueishan, taoyuan, taiwan, r.o.c. the nanya technology corporation home page can be f ound at http:\\www.nanya.com ? |
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